1. Field of the Invention
The present invention relates to a reliable, efficient method for reducing oxidized metal; a multilayer interconnection structure with reduced interconnection resistance where parasitic capacities between interconnections can be reduced with the method, and an efficient method for manufacturing the same; and a high-speed, highly-reliable semiconductor device having the multilayer interconnection structure, and an efficient method for manufacturing the same. More particularly, the present invention relates to a method for reducing copper oxide for reducing copper interconnections efficiently, reliably and inexpensively during the formation of a multilayer interconnection structure of a semiconductor integrated circuit.
2. Description of the Related Art
As the scale of integration of semiconductor integrated circuits and chip density have been increasing, so too has been, in particular, a demand to provide a multilayer structure of semiconductor chips. Against this background, the interval between adjacent interconnections, or interconnection interval, has become smaller and smaller, leading to a problem of interconnection delay due to increased capacities between interconnections. Here, the interconnection delay (T) is represented by the equation T ∝ RC, which means that (T) is influenced by the interconnection resistance (R) and the capacity between adjacent interconnections (C). The relationship between permittivity (ε) and capacity (C) is represented by the equation C=ε0εr ·S/d (where S is an electrode area, so is the permittivity of vacuum, εr is the permittivity of an insulating film, and d is the interconnection interval). The reduction of capacity (C) can be achieved by reducing the interconnection thickness and electrode area, though, reducing the interconnection thickness causes an increase in the interconnection resistance (R), making it impossible to achieve speedup of the device. Accordingly, reducing both the permittivity of insulating films and the interconnection resistance is the effective way to achieve speedup by minimizing the interconnection delay (T).
In a semiconductor device with a multilayer interconnection structure, the interval between adjacent interconnections has become smaller and smaller, with the recent trend moving toward an increased scale of integration of semiconductor integrated circuits and greater chip density, thus leading to an increased impedance of metal interconnections due to electrostatic induction. For this reason, there is a great concern that response speed will be reduced and power consumption will be increased. To avoid this problem, it is necessary to reduce the permittivities of interlayer insulating films as small as possible, which are provided between the semiconductor substrate and metal interconnections or between interconnection layers.
Materials for conventional insulating films include inorganic materials such as silicon dioxide (SiO2), silicon nitride (SiN) and phosphosilicate glass (PSG), and organic high-molecular materials such as polyimides. The CVD-SiO2 film, an insulating film often used in semiconductor devices, however, has a permittivity of as high as 4. In addition, the SiOF film, an insulating film that has been studied as a candidate for a low-permittivity CVD film, has a permittivity of as small as 3.3 to 3.5, but highly hygroscopic; therefore, it has a problem that permittivity increases with time.
Moreover, for example, a porous silica-based low-permittivity film has been proposed (see Japanese Patent Application Laid-Open UP-A) No. 2004-153147) as a low-permittivity film. The production process for this film involves a pore formation step in which thermally decomposable components (e.g., organic resins that are evaporated or decomposed by heat) are added to a film formation material, and evaporated or decomposed by heat upon film deposition to thereby form pores therein. Thus, it is possible to further achieve permittivity reduction.
The pore size of this sort of porous film, however, is large—10 nm or more when produced using currently available methods. For this reason, increasing the porosity for reduced permittivity leads to a problem of increased permittivity and/or reduced film strength, which are caused due to moisture absorption. Moreover, although organic polymer films can be cited as films with excellent moisture resistance, their glass transition temperature is as low as 200° C. to 350° C. and their coefficient of thermal expansion is high. For this reason, they have a problem that they can damage interconnections.
Meanwhile, since the interconnection resistance decreases inversely with the interconnection volume, an increase in the interconnection resistance associated with finer interconnections cannot be avoided. In recent years, however, influences of the contact resistance of vias through which vertically adjacent interconnections of a multilayer interconnection structure are connected together have become a more serious problem than this interconnection resistance increase. More specifically, the surface of the interconnections to be connected to the vias is unfavorably oxidized to increase their contact resistance.
To solve this problem, copper oxide present at the surface of the interconnections to be connected to the vias needs to be reduced to copper. However, conventional annealing approaches performed under reduction gas (e.g., ammonia gas and hydrogen gas) atmosphere cannot achieve satisfactory reduction.
In addition, reduction methods using ammonia plasma or hydrogen plasma can be used; however, such methods damage low-permittivity insulating films to result in increased permittivity.
Furthermore, a method has been proposed in which an organic acid such as formic acid or acetic acid is gasified and the resultant gas is used as reduction gas (see, for example, Japanese Patent Application Laid-Open (JP-A) No. 2004-71705). When forming interconnections by depositing metal such as copper on the surface of a silicon wafer or the like using a CVD apparatus with this method, a thin metal film is formed also on the inner wall of the chamber. This thin metal film is chelated by the reduction gas, sublimated, and exhausted out of the chamber.
This method, however, is only intended for the removal of the thin metal film attached to the inner wall of the chamber; this Patent Literature fails to disclose or suggest a method for reducing the surface of oxidized interconnections and its effects.
In contrast to the foregoing plasma reduction method, this method can achieve reduction of the surface of interconnections that are formed on a silicon wafer or the like without increasing the permittivities of films, though, it is difficult to control the reduction rate because the reduction reaction is rapid. Moreover, this method has a problem that the gasified organic acid forms a dimer, which reacts with copper and scatters it over the surface of the silicon wafer or the like.
It is an object of the present invention to solve the foregoing problems and to achieve the object described below.
Specifically, it is an object of the present invention to provide a reliable, efficient method for reducing oxidized metal; a multilayer interconnection structure with reduced interconnection resistance where parasitic capacities between interconnections can be reduced with the method, and an efficient method for manufacturing the same; and a high-speed, highly-reliable semiconductor device having the multilayer interconnection structure, and an efficient method for manufacturing the same. More particularly, the present invention relates to a method for reducing copper oxide for reducing copper interconnections efficiently, reliably and inexpensively during the formation of a multilayer interconnection structure of a semiconductor integrated circuit.